Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features
US7906254B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2007 |
| Grant date | Mar 15, 2011 |
| Priority date | — |
| Expiry date | Mar 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.