Andrzej Strojwas
84Patents
6h-index
28Co-inventors
68Inventor score
Filing activity: Nov 4, 2005 → Jun 30, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7278118B2 | Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features | Physics | 204 | Expired |
| US9799575B2 | Integrated circuit containing DOEs of NCEM-enabled fill cells | Electricity | 17 | Active |
| US9805994B1 | Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads | Electricity | 13 | Active |
| US9870962B1 | Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Electricity | 12 | Active |
| US9627370B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells | Electricity | 11 | Active |
| US10593604B1 | Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells | Electricity | 8 | Active |
| US9627371B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells | Electricity | 5 | Active |
| US9691672B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells | Electricity | 4 | Active |
| US10978438B1 | IC with test structures and E-beam pads embedded within a contiguous standard cell area | Electricity | 4 | Active |
| US9773774B1 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells | Electricity | 3 | Active |
| US10096530B1 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells | Electricity | 3 | Active |
| US10199283B1 | Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage | Electricity | 3 | Active |
| US9741703B1 | Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including at least via-open-configured, gate-short-configured, TS-short-configured, and AA-short-conigured, NCEM-enabled fill cells | Electricity | 3 | Active |
| US9653446B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and AA-short-configured, NCEM-enabled fill cells | Electricity | 2 | Active |
| US9761575B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells | Electricity | 2 | Active |
| US9911649B1 | Process for making and using mesh-style NCEM pads | Electricity | 2 | Active |
| US9786648B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells | Electricity | 2 | Active |
| US9728553B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells | Electricity | 1 | Active |
| US9929063B1 | Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Electricity | 1 | Active |
| US9905487B1 | Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opens | Electricity | 1 | Active |
| US9711421B1 | Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of GATE-snake-open-configured, NCEM-enabled fill cells | Electricity | 1 | Active |
| US9922968B1 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells | Electricity | 1 | Active |
| US9768083B1 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells | Electricity | 1 | Active |
| US9646961B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and metal-short-configured, NCEM-enabled fill cells | Electricity | 1 | Active |
| US9947601B1 | Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.