Method for integrating silicon-on-nothing devices with standard CMOS devices
US7906381B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 3, 2008 |
| Grant date | Mar 15, 2011 |
| Priority date | — |
| Expiry date | Apr 26, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D87/00
Abstract
A method is provided for fabricating transistors of first and second types in a single substrate. First and second active zones of the substrate are delimited by lateral isolation trench regions, and a portion of the second active zone is removed so that the second active zone is below the first active zone. First and second layers of semiconductor material are formed on the second active zone, so that the second layer is substantially in the same plane as the first active zone. Insulated gates are produced on the first active zone and the second layer. At least one isolation trench region is selectively removed, and the first layer is selectively removed so as to form a tunnel under the second layer. The tunnel is filled with a dielectric material to insulate the second layer from the second active zone of the substrate. Also provided is such an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.