SOI transistor with self-aligned ground plane and gate and buried oxide of variable thickness
US7910419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2009 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | Jun 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0323
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a transistor with self-aligned gate and ground plane includes forming a stack, on one face of a semi-conductor substrate, the stack including an organometallic layer and a dielectric layer. The method also includes exposing a part of the organometallic layer, a portion of the organometallic layer different to the exposed part being protected from the electron beams by a mask, the shape and the dimensions of a section, in a plane parallel to the face of the substrate, of the gate of the transistor being substantially equal to the shape and to the dimensions of a section of the organometallic portion in said plane. The method also includes removing the exposed part, and forming dielectric portions in empty spaces formed by the removal of the exposed part of the organometallic layer, around the organometallic portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.