Time-of-life counter for handling instruction flushes from a queue
US7913070B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2008 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | May 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.