Method and apparatus for receive channel data alignment with minimized latency variation
US7913104B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 12, 2007 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | Dec 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/062
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Data and clock synchronization within a gigabit receiver is maintained throughout the data byte processing logic of the receiver by utilizing the same byte clock signal. The deserialization clock signal that is used to deserialize the received serial data stream is phase coherent with the distributed byte clock signal used within the physical coding sublayer (PCS), thus establishing reliable data transfer across the physical media attachment (PMA) and PCS layers of the gigabit receiver while maintaining a known, fixed latency. The phase relationship between a derived bit clock signal and the byte clock signal is shifted in a manner that achieves coarse data alignment within each data byte without affecting the latency. Conversely, the coarse data alignment is combined with a data alignment toggling procedure to reduce data alignment granularity with minimized latency changes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.