Method of verifying a layout pattern
US7913196B2 · kind B2 · utility
3Cited by
4References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2007 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | Sep 7, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of verifying a layout pattern comprises separately steps of obtaining a simulated pattern at a lower portion of a film by using a layout pattern as a mask to transfer the layout pattern to the film, and obtaining a simulated pattern at an upper portion of the film by using the layout pattern as a mask to transfer the layout pattern to the film. The layout pattern is verified according to the upper and lower simulated patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.