Dual charge storage node memory device and methods for fabricating such device
US7915123B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2006 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Mar 3, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/954
Abstract
A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.