Integrated circuits having a contact region and methods for manufacturing the same
US7915667B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2008 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | May 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
Abstract
In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.