Delay locked loop circuit and operational method thereof
US7915934B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 21, 2009 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | May 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop circuit includes a clock buffering block to generate first and second internal clocks corresponding to first and second edges of a source clock in response to a clock buffering control signal, respectively, wherein generation of the second internal clock is controlled by a duty correcting operation terminating signal and a delay locking signal, a delay locking block to compare phases of the first and second internal clocks with those of first and second feedback clocks, respectively, to enable the delay locking signal according to a delay locking and delay the first and second internal clocks as many as times corresponding to the comparison results, respectively, thereby outputting first and second delay locking clocks, a duty correcting block to mix phases of the first and second delay locking clocks, and a first signal generating block to generate the duty correcting operation terminating signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.