Method and system for rapid evaluation of logical expressions
US7917455B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2009 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Nov 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems capable of determining which subset of a set of logical expressions are true with relatively few evaluations of the primitives that together with any standard logical connectives, make up the logical expressions. A plurality of directed acyclic graphs, each graph including at least one root node, at least one leaf node, and at least one non-leaf node associated with a leaf node. Each node is associated with a, possibly empty, subset of presumed to be true logical expressions. Each non-leaf node is associated with one of the primitives mentioned in any of the logical expressions. Edges are defined between two of the nodes, each edge being associated with a possible value, or range of possible values, of the primitive associated with the node at the tail of the edge. Paths are defined through each of the directed acyclic graphs from a root node to a leaf node by recursively following each edge corresponding to the current value of the primitive at a selected non-leaf node. Lastly, subsets of logical expressions associated with the nodes on the defined paths are collated to yield a subset of logical expressions that are true.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.