Virtualization assist for legacy x86 floating point exception handling
US7917740B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2005 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Jan 19, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45533
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor comprises an execution core configured to detect a freeze event responsive to an error indication, an ignore error indication, and an instruction in a guest. The instruction belongs to a predefined subset of instructions associated with the error indication and the ignore error indication. The execution core is configured to exit the guest in response to detecting the freeze event. In some embodiments, the error indication and the ignore indication may be stored in one or more registers in the processor. In some embodiments, the instruction is a floating point instruction, the error indication is a floating pointer error indication, and the ignore error indication is an ignore floating point error indication. In some embodiments, the error indication may correspond to an error signal output by the processor, and the ignore error indication may correspond to an ignore error signal input to the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.