Method for forming oxide on ONO structure
US7919372B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2007 |
| Grant date | Apr 5, 2011 |
| Priority date | — |
| Expiry date | Mar 7, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/954
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures. Exposing the patterned silicon nitride to the oxygen radical during the RTO according to the invention significantly reduces the processing time, and reduces the thermal budget. Moreover, because according to the invention the upper surface and the sidewalls of the silicon n…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.