Method of high density field induced MRAM process
US7919407B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2009 |
| Grant date | Apr 5, 2011 |
| Priority date | — |
| Expiry date | Nov 17, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described herein are novel, cost effective and scalable methods for integrating a CMOS level with a memory cell level to form a field induced MRAM device. The memory portion of the device includes N parallel word lines, which may be clad, overlaid by M parallel bit lines orthogonal to the word lines and individual patterned memory cells formed on previously patterned electrodes at the N×M intersections of the two sets of lines. The memory portion is integrated with a CMOS level and the connection between levels is facilitated by the formation of interconnecting vias between the N×M electrodes and corresponding pads in the CMOS level and by word line connection pads in the memory device level and corresponding metal pads in the CMOS level. Of particular importance are process steps that replace single damascene formations by dual damascene formations, different process steps for the formation of clad and unclad word lines and the formation of patterned electrodes for the memory cells prior to the patterning of the cells themselves.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.