Manufacturing method for planar independent-gate or gate-all-around transistors
US7923315B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2008 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Dec 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
Abstract
The present invention relates to a method for fabricating a planar independent-double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.