Method for gap filling in a gate last process

US7923321B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Su-Chen Lai · Hsinchu, TW
• Kong-Beng Thei · Baoshan, TW
• Harry-Hak-Lay Chuang · Austin, US
• Gary Shen · Sanwan, TW

Key dates

• Filing date: Jun 19, 2009
• Grant date: Apr 12, 2011
• Expiry date: Jul 25, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/691

Abstract

A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the substrate, forming a silicon layer over the high-k dielectric layer, forming a hard mask layer over the silicon layer, patterning the hard mask layer, silicon layer, and high-k dielectric layer to form first and second gate structures over the first and second regions, respectively, forming a contact etch stop layer (CESL) over the first and second gate structures, modifying a profile of the CESL by an etching process, forming an inter-layer dielectric (ILD) over the modified CESL, performing a chemical mechanical polishing (CMP) on the ILD to expose the silicon layer of the first and second gate structures, respectively, and removing the silicon layer from the first and second gate structures, respectively, and replacing it with metal gate structures.