Fin field effect transistor devices with self-aligned source and drain regions

US7923337B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Josephine B. Chang · Mahopac, US
• Michael A. Guillorn · Locke, US
• Wilfried E. Haensch · Somers, US
• Katherine L. Saenger · Ossining, US

Key dates

• Filing date: Jun 20, 2007
• Grant date: Apr 12, 2011
• Expiry date: Jan 29, 2028

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/938

Abstract

Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a field effect transistor device comprises the following steps. A substrate is provided having a silicon layer thereon. A fin lithography hardmask is patterned on the silicon layer. A dummy gate structure is placed over a central portion of the fin lithography hardmask. A tiller layer is deposited around the dummy gate structure. The dummy gate structure is removed to reveal a trench in the filler layer, centered over the central portion of the fin lithography hardmask, that distinguishes a fin region of the device from source and drain regions of the device. The fin lithography hardmask in the fin region is used to etch a plurality of fins in the silicon layer. The trench is filled with a gate material to form a gate stack over the fins. The filler layer is removed to reveal the source and drain regions of the device, wherein the source and drain regions are intact and self-aligned with the gate stack.