Increasing stress transfer efficiency in a transistor by reducing spacer width during the drain/source implantation sequence

US7923338B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Maciej Wiatr · Dresden, DE
• Roman Boschke · Dresden, DE
• Anthony Mowry · Kyle, US

Key dates

• Filing date: Nov 14, 2008
• Grant date: Apr 12, 2011
• Expiry date: Nov 14, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

By forming a single spacer element and reducing the size thereof by a well-controllable etch process, a complex lateral dopant profile may be obtained at reduced process complexity compared to conventional triple spacer approaches in forming drain and source regions of advanced MOS transistors.