Inventor · Dresden, DE

Roman Boschke

34Patents

4h-index

31Co-inventors

59Inventor score

Filing activity: Mar 21, 2007 → Dec 16, 2016

Most-cited inventions

Patent	Title	Area	Cited by	Status
US9515155B2	E-fuse design for high-K metal-gate technology	Electricity	9	Active
US8497180B2	Transistor with boot shaped source/drain regions	Electricity	8	Active
US8609498B2	Transistor with embedded Si/Ge material having reduced offset and superior uniformity	Electricity	5	Active
US8617940B2	SOI device with a buried insulating material having increased etch resistivity	Electricity	4	Active
US8962420B2	Semiconductor device comprising a buried poly resistor	Electricity	4	Active
US8338892B2	Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by corner rounding at the top of the gate electrode	Electricity	3	Active
US9431508B2	Simplified gate-first HKMG manufacturing flow	Electricity	3	Active
US8268679B2	Semiconductor device comprising eFUSES of enhanced programming efficiency	Emerging Cross-Sectional Technologies	3	Active
US9450073B2	SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto	Electricity	2	Active
US8735241B1	Semiconductor device structure and methods for forming a CMOS integrated circuit structure	Electricity	2	Active
US9006835B2	Transistor with embedded Si/Ge material having reduced offset and superior uniformity	Electricity	2	Active
US8373244B2	Temperature monitoring in a semiconductor device by thermocouples distributed in the contact structure	Electricity	2	Active
US8097519B2	SOI device having a substrate diode formed by reduced implantation energy	Electricity	2	Active
US8939765B2	Reduction of defect rates in PFET transistors comprising a Si/Ge semiconductor material formed by epitaxial growth	Electricity	2	Active
US8481404B2	Leakage control in field effect transistors based on an implantation species introduced locally at the STI edge	Electricity	2	Active
US7569437B2	Formation of transistor having a strained channel region including a performance enhancing material composition utilizing a mask pattern	Electricity	2	Active
US7879667B2	Blocking pre-amorphization of a gate electrode of a transistor	Electricity	2	Active
US7964458B2	Method for forming a strained transistor by stress memorization based on a stressed implantation mask	Electricity	1	Active
US9117929B2	Method for forming a strained transistor by stress memorization based on a stressed implantation mask	Electricity	1	Active
US7923338B2	Increasing stress transfer efficiency in a transistor by reducing spacer width during the drain/source implantation sequence	Electricity	0	Active
US8652913B2	Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss	Electricity	0	Active
US8697584B2	Enhanced transistor performance of N-channel transistors by using an additional layer above a dual stress liner in a semiconductor device	Electricity	0	Active
US8334573B2	Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices	Electricity	0	Active
US8664049B2	Semiconductor element formed in a crystalline substrate material and comprising an embedded in situ doped semiconductor material	Electricity	0	Active
US9659928B2	Semiconductor device having a high-K gate dielectric above an STI region	Emerging Cross-Sectional Technologies	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.