Method to reduce collector resistance of a bipolar transistor and integration into a standard CMOS flow
US7923340B2 · kind B2 · utility
4Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2007 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Feb 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0109
Abstract
The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.