Gate structures in semiconductor devices
US7928498B2 · kind B2 · utility
1Cited by
3References
2Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 22, 2009 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Apr 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
Abstract
A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.