Protection against charging damage in hybrid orientation transistors

US7928513B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Terence B. Hook · Jericho, US
• Anda C. Mocuta · Hopewell Junction, US
• Jeffrey W. Sleight · Ridgefield, US
• Anthony K. Stamper · Williston, US

Key dates

• Filing date: Dec 22, 2008
• Grant date: Apr 19, 2011
• Expiry date: Apr 8, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/601

Abstract

A chip can include a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. An SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a di…