Compact virtual ground diffusion programmable ROM array architecture, system and method
US7929347B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2009 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Oct 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.