Method for manufacturing a stacked semiconductor package, and stacked semiconductor package
US7932162B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2008 |
| Grant date | Apr 26, 2011 |
| Priority date | — |
| Expiry date | Jul 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer; processing the wafer so as to obtain the plurality of semiconductor chips; subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.