Electronic devices including solder bumps on compliant dielectric layers
US7932615B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 5, 2007 |
| Grant date | Apr 26, 2011 |
| Priority date | — |
| Expiry date | Sep 23, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic device may include a substrate with an input/output pad thereon, and a compliant dielectric layer on a first portion of the substrate such that a second portion of the substrate is free of the compliant dielectric layer. A conductive redistribution line may extend from the input/output pad to the compliant dielectric layer so that the compliant dielectric layer is between a bump pad portion of the conductive redistribution line and the substrate. A first solder bump may be on the bump pad portion of the conductive redistribution line so that the compliant dielectric layer is between the first solder bump and the substrate. A second solder bump may be on the second portion of the substrate that is free of the compliant dielectric layer. Related methods are also discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.