Low power mode unipolar current/voltage mode interface
US7934109B2 · kind B2 · utility
2Cited by
9References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2007 |
| Grant date | Apr 26, 2011 |
| Priority date | — |
| Expiry date | Jun 9, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.