Legalization of VLSI circuit placement with blockages using hierarchical row slicing
US7934188B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2008 |
| Grant date | Apr 26, 2011 |
| Priority date | — |
| Expiry date | May 29, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and the large blockages without regard to small blockages (while satisfying capacity constraints of the coarse regions), and thereafter the movable logic cells are relocated among fine regions between small blockages to remove all cell overlaps (while satisfying capacity constraints of the fine regions). The coarse and fine regions may be horizontal slices of the placement region having a height corresponding to a single circuit row height of the design. Cells are relocated with minimal perturbation from the previous placement, preserving wirelength and timing optimizations. The legalization technique may utilize more than two levels of granularity with multiple relocation stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.