Semiconductor device and manufacturing method of the same
US7935597B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2010 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Oct 26, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.