Selective refresh of single bit memory cells
US7936610B1 · kind B1 · utility
22Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2009 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Oct 28, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems to selectively refresh a single bit per cell non-volatile memory cell to reduce memory cell errors. In an embodiment, a memory device scans its memory cells, performing a multi-level read on memory cells in a single bit per cell mode. Depending on the state sensed, the cell is refreshed to a correct state if necessary. In one embodiment, the memory scan is appended to a user erase operation, a flash block is swapped with another bock if the state sensed indicates charge gain, and a flash cell is programmed up if the state sensed indicates charge loss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.