Configuration of a multi-level flash memory device
US7937576B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2006 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Jan 29, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.