Design-for-test-aware hierarchical design planning
US7937677B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2008 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Jul 16, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Full-chip scan data can be advantageously used during design planning to minimize top-level scan wires and scan feedthroughs. The scan cells can be reordered using a modified cost function to promote connecting all scan cells in one plan group before crossing to a scan cell in another plan group. The modified cost function can take into account penalty parameters. The penalty parameters can include at least one of: membership in a plan group or a top-level physical hierarchy, size of a plan group, FLOATING/ORDERED scan element in scan data, location of endpoints of an ORDERED list, location of endpoints of a macro, and membership in a plan group containing a STOP point. Scan data, at the block-level and at the top-level, can be automatically updated to reflect the plan groups and optimized scan chains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.