Register controlled delay locked loop circuit
US7940096B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2008 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Apr 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A register controlled DLL circuit occupies a relatively small area in a semiconductor device by reducing the number of flip-flops for generating timing pulses that are used to control a DLL operation and sequentially toggled. The registered controlled DLL circuit for generating a DLL clock by delaying internal clocks includes a timing pre-pulse generating unit configured to generate a plurality of timing pre-pulses activated sequentially in response to a source clock, the plurality of pre-pulses being repeated two or more times in each delay shifting update period, a mask signal generating unit configured to generating a mask signal having a logic level varied according to toggling of a predetermined one of the timing pre-pulses, and a timing pulse outputting unit configured to output the plurality of timing pre-pulses as a plurality of timing pulses in response to the mask signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.