Low power read scheme for read only memory (ROM)
US7940545B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2009 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Dec 16, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ROM includes a ROM array, an address decoder, a control circuit, a precharge tracker, a precharge circuit, a reference word line, a reference bit line and a reference sense generator. The control circuit generates control signals for reading the ROM. The address decoder enables a bit line and a word line. The precharge tracker generates a programmable precharge signal, which is provided to the precharge circuit for precharging the enabled bit line. A reference word line is enabled based on the programmable precharge signal and the control signals for tracking the enabled word line. A reference bit line is enabled based on the reference word line for tracking the enabled bit line. The reference sense generator generates a programmable sense signal based on the reference bit line, the programmable precharge signal and the control signals for reading a bit cell corresponding to the enabled bit line and word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.