Systems and methods for reducing memory array leakage in high capacity memories by selective biasing
US7940550B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2009 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Nov 7, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A source-biasing mechanism for leakage reduction in SRAM in which SRAM cells are arranged into a plurality of sectors. In standby mode, the SRAM cells in a sector in the plurality of sectors are deselected and a source-biasing potential is provided to the SRAM cells of the plurality sectors. In working mode, the source-biasing potential provided to the SRAM cells of a selected sector in the plurality of sectors is deactivated and the SRAM cells in a physical row within the selected sector are read while the remaining SRAM cells in the unselected sectors continue to be source-biased. The source-biasing potential provided to the SRAM cells that are in standby mode can be set to different voltages based on the logical state of control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.