Dynamic critical path detector for digital logic circuit paths

US7941772B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Serafino Bueti · Waterbury, US
• Kenneth J. Goodnow · South Burlington, US
• Todd E. Leonard · Williston, US
• Gregory J. Mann · Colorado Springs, US
• Peter A. Sandon · South Burlington, US
• Peter A. Twombly · Shelburne, US
• Charles S. Woodruff · Vergennes, US

Key dates

• Filing date: Aug 6, 2007
• Grant date: May 10, 2011
• Expiry date: Jan 17, 2030

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path.