Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom

US7943456B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Shaofeng Yu · Plano, US
• Freidoon Mehrad · Plano, US
• Brian K. Kirkpatrick · Allen, US

Key dates

• Filing date: Dec 31, 2008
• Grant date: May 17, 2011
• Expiry date: Dec 31, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822

Abstract

A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes providing a substrate having a semiconductor surface including PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate stack including a gate electrode layer is formed on a gate dielectric layer in or on both the PMOS regions and the NMOS regions. An n-type doping is used to create n-type wet etch sensitized regions on opposing sides of the gate stack in both the PMOS and said NMOS regions. Wet etching removes the n-type wet etch sensitized regions in (i) at least a portion of said PMOS regions to form a plurality of PMOS source/drain recesses or (ii) in at least a portion of said NMOS regions to form a plurality of NMOS source/drain recesses, or (i) and (ii). At least one of a compressive strain inducing epitaxial layer is formed in the plurality of PMOS source/drain recesses and a tensile strain inducing epitaxial layer is formed in the plurality of NMOS source/drain recesses. The fabrication of the IC is then completed.