Integration of high-k metal gate stack into direct silicon bonding (DSB) hybrid orientation technology (HOT) pMOS process flow
US7943479B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Aug 19, 2008 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Jul 30, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation layer, and a second crystal orientation layer, and a border region disposed between the first and second crystal orientations. A high-k metal gate stack is deposited over the first crystal orientation layer that comprises an insulation layer, a high-k dielectric layer, a first metal layer, and a second metal layer thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.