Circuit for generating negative voltage and semiconductor memory apparatus using the same
US7944278B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2008 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Dec 23, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for generating negative voltage of a semiconductor memory apparatus includes a first detecting unit configured to generate a first detecting signal by detecting a first negative voltage level, a first negative voltage generating unit configured to generate the first negative voltage in response to the first detecting signal, a second detecting unit configured to generate a second detecting signal by detecting the second negative voltage level, a timing controlling unit configured to output the second detecting signal as an enable signal when a power up signal is enabled and the first detecting signal is disabled, and a second negative voltage generating unit configured to generate the second negative voltage in response to the enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.