Stream based stimulus definition and delivery via interworking

US7945418B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Mrinal Bose · Austin, US
• Jayanta Bhadra · Austin, US
• Kenneth G. Davis · Woodville, US
• Yaniv Fais · Kiryat Yam, IL
• Sharon Goldschlager · Nes Ziona, IL
• Amit Hermony · Givat Ada, IL
• Hillel Miller · Austin, US
• Prashant U. Naphade · Cedar Park, US
• Pankaj Sharma · New Delhi, IN
• Robert S. Slater · Raanana, IL

Key dates

• Filing date: Dec 15, 2008
• Grant date: May 17, 2011
• Expiry date: Aug 3, 2029

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/26
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set of transactors sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor.