Asymmetric single poly NMOS non-volatile memory cell
US7948020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2010 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Mar 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an elongated floating gate having a first portion disposed over the channel region C150, a second portion extending into an enlarged drain diffusion area D150 away from the channel region, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitance. The width of the floating gate extension portion is minimized, while both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. HV LDD implant in the NVM transistor is replaced by LV LDD. The floating gate is formed using substantially U-shaped or J-shaped polysilicon structures. Various array addressing schemes are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.