Inventor · San Jose, CA, US

Ishai Naveh

15Patents

5h-index

12Co-inventors

59Inventor score

Filing activity: Feb 25, 2008 → Mar 12, 2019

Most-cited inventions

Patent	Title	Area	Cited by	Status
US7800156B2	Asymmetric single poly NMOS non-volatile memory cell	Electricity	26	Active
US8687403B1	Circuits having programmable impedance elements	Physics	24	Active
US7948020B2	Asymmetric single poly NMOS non-volatile memory cell	Electricity	15	Active
US8947913B1	Circuits and methods having programmable impedance elements	Physics	8	Active
US8913444B1	Read operations and circuits for memory devices having programmable elements, including programmable resistance elements	Physics	6	Active
US9812183B2	Read latency reduction in a memory device	Physics	4	Active
US8675396B1	Integrated circuit devices and systems having programmable impedance elements with different response types	Physics	4	Active
US10290334B2	Read latency reduction in a memory device	Physics	3	Active
US10726888B2	Read latency reduction in a memory device	Physics	3	Active
US9343667B1	Circuits having programmable impedance elements and vertical access devices	Physics	2	Active
US9755142B1	Methods of making memory devices with programmable impedance elements and vertically formed access devices	Physics	1	Active
US10984861B1	Reference circuits and methods for resistive memories	Physics	1	Active
US9570166B1	Read operations and circuits for memory devices having programmable elements, including programmable resistance elements	Physics	1	Active
US8902631B2	Memory devices, circuits and, methods that apply different electrical conditions in access operations	Physics	1	Active
US9373398B1	Prototyping integrated circuit devices with programmable impedance elements	Physics	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.