Structure and method of sub-gate NAND memory with bandgap engineered SONOS devices
US7948799B2 · kind B2 · utility
30Cited by
30References
13Claims
0Family size
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Key dates
| Filing date | Jul 17, 2008 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | May 17, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bandgap engineered SONOS device structure for design with various AND architectures. The BE-SONOS device structure comprises a spacer oxide disposed between a control gate overlaying an oxide-nitride-oxide-nitride-oxide stack and a sub-gate overlaying a gate oxide. In one example, a BE-SONOS sub-gate-AND array architecture has multiple strings of SONONOS devices with sub-gate lines and diffusion bit lines. In another example, a BE-SONOS sub-gate-AND architecture has multiple strings of SONONOS devices with sub-gate lines, relying on the sub-gate lines that create inversions to substitute for the diffusion bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.