Process for wafer temperature verification in etch tools
US7951616B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2009 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Oct 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A blank wafer is placed in an etch chamber. A layer is deposited over the blank wafer, comprising providing a deposition gas, forming the deposition gas into a deposition plasma, and stopping the deposition gas. The blank wafer with the deposited layer is removed from the etch chamber. The thickness of the deposited layer is measured. Wafer temperature accuracy is calculated from the measured thickness of the deposited layer. The etch chamber is compensated according to the calculated wafer temperature accuracy. A wafer with an etch layer over the wafer and a patterned mask over the etch layer is placed into the etch chamber. The etch layer is etched in the etch chamber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.