Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor
US7951657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2009 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Aug 8, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/364
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.