SI trench between bitline HDP for BVDSS improvement
US7951675B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2007 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | May 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the semiconductor substrate between the first spacers; and second spacers adjacent the side surfaces of the trench. By containing the trench and the first and second spacers between the bitlines, the memory device can improve the electrical isolation between the bitlines, thereby preventing and/or mitigating bitline-to-bitline current leakage and increasing BVdss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.