In-situ process layer using silicon-rich-oxide for etch selectivity in high AR gapfill
US7951683B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 6, 2007 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Sep 11, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76837
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots is provided. This deposition part of the process may involve the use of any suitable high density plasma chemical vapor deposition (HDP CVD) chemistry. Prior to etch back, the feature gap is plugged with an etch selectivity layer. The etch back part of the process involves multiple steps including a sputter etch to reduce the top hat formations followed by a reactive plasma etch to open the gap. This method improves gapfill, reduces the use of high cost fluorine-based etching and produces interim gaps with better sidewall profiles and aspect ratios.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.