Multiple embedded memories and testing components for the same
US7954017B2 · kind B2 · utility
6Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Nov 28, 2006 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Mar 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.