Single bit line SMT MRAM array architecture and the programming method
US7957183B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 4, 2009 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Dec 24, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SMT MRAM device includes a plurality of SMT MRAM cells arranged in an array of rows and columns. Single bit lines connect the columns of the SMT MRAM cells for receiving an in-phase data signal. Source lines connect pairs of rows of the SMT MRAM cells for receiving an out-of-phase data signal. Out-of-phase switching devices are connected to the source lines for selectively transferring the out-of-phase signal to the at least one source lines. Column select transistors are connected to the single bit lines for transferring an in-phase data signal to a selected column of the SMT MRAM cells. A precharge circuit selectively charges or discharges the single bit lines. Ground switching devices selectively connect to the source lines to a ground reference voltage source. A method for programming a selected SMT MRAM cell within a provided SMT MRAM device is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.