Flash memory programming power reduction
US7957204B1 · kind B1 · utility
10Cited by
36References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2005 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Sep 20, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.