Operation method for multi-level switching of metal-oxide based RRAM
US7960224B2 · kind B2 · utility
14Cited by
4References
15Claims
0Family size
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Key dates
| Filing date | Feb 19, 2009 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Apr 30, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a memory device includes applying a sequence of bias arrangements across a selected metal-oxide memory element to change among resistance states. The sequence of bias arrangements includes a first set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the first resistance state to a third resistance state, and a second set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the third resistance state to the second resistance state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.